1. Field of the Invention
The invention relates generally to computer interfacing and specifically to local area networks (LANs) with many client workstations that communicate with one or more network servers, such as where the LANs have parallel segments.
2. Description of the Prior Art
Personal computers and engineering workstations are conventionally inter-tied into local area networks (LANs) that allow messages to be sent and programs to be downloaded, e.g., from file servers on the LAN. The ETHERNET, originally a joint effort of Intel, Xerox and Digital Equipment Corporations, is an example of a shared-access LAN now in widespread use. The ETHERNET was originally conceived as a ten megabit per second (Mbps) network that allowed every node on the LAN to transmit and receive. Collisions of data occur when two nodes try to transmit at the same time. Such conflicts are resolved by postponing each's retransmission after a random waiting period.
Many variations in ETHERNET have been subsequently developed. Different kinds of ETHERNET are referred to as "10BASE-T", "10BASE-2", "10BASE-5", "100BASE-VG", and "100BASE-X". Different speeds include ten Mbps, twenty Mbps, one hundred Mbps, and beyond. Different modes of ETHERNET also exist, e.g., conventional half-duplex, and full-duplex ETHERNET switch (FDES). The present invention contributes a new collisionless mode and operational speeds as high as 320 Mbps.
Faster engineering workstations and distributed file systems, such as NFS, LAN MANAGER, and NETWARE, have seriously increased the traffic placed on ordinary LANs. Network congestion results in long processing delays and broken connections. Bridging allows one large LAN to be divided into several parallel segments that are interconnected by a bridge. Intra-segment traffic is conducted in parallel amongst the several segments. It is advantageous therefore to gerrymander the LAN for a minimum amount of inter-segment traffic bridging. The store and forward limitation of such bridging takes time and can cause transmit delays for messages moving from one segment to another. Routers allow individual LANs to be inter-tied. Routers are used with protocols such as ICMP to report inter-network congestion and other anomalous conditions back to end nodes.
Single-chip integrated circuit devices are sold commercially that provide the ETHERNET function in a convenient form that is easy to integrate on to a plug-in LAN adapter board. Such network interface controllers (NICs) make no distinction between the interface of a server and a client. However, servers are typically at the focus of network activity and are often subjected to parallel access requests from clients which have the same data transfer speed limitations as the server itself.
A systems-oriented network interface controller (SONIC) with a twisted pair interface is marketed by National Semiconductor (Santa Clara, Calif.) in a single integrated circuit as the "DP83934 SONIC.TM.-T". The SONIC-T is a second generation ETHERNET controller for sixteen and thirty-two bit system interfacing. A high speed direct memory access (DMA) controller takes five percent of the bus bandwidth and selectable bus mode provide for big-endian and little-endian byte ordering. A linked-list buffer manager permits a range of uses from personal computer (PC) oriented adapters to high-speed motherboard designs. A fully compatible Institute of Electrical and Electronic Engineers (IEEE) standard number 802.3 (IEEE 802.3) encoder/decoder (ENDEC) and a twisted pair interface (TPI) allow a one chip 10BASE-T ETHERNET solution. A National DP8392 coaxial transceiver interface permits the construction of 10BASE2 or 10BASE5 systems. The buffer manager processes receive and transmit packets in the system memory, therefore eliminating intermediate packet copying. The receive buffer manager uses three areas in memory for additional resource allocation, status indication, and packet data buffering. The SONIC-T stores received packets in the buffer area and indicates the receive status and control information in a descriptor area. The transmit buffer manager uses two memory areas, one for status and control indication and the other for fetching packet data.
Conventional SONIC single-chip devices include a TPI, an ENDEC, a media access controller (MAC) unit, separate receive and transmit first-in first-out (FIFO) registers, a system buffer management engine and a user programmable system bus interface unit. Pipelined architectures are used to increase system-level performance. The TPI has five main logic units: a smart squelch, a collision detector, a link detector/generator, a jabber and a transmitter. The smart squelch determines if valid data is present at the inputs. The collision detector checks for simultaneous data transmission and reception on the inputs and outputs. The link detector/generator checks the cable integrity. The jabber prevents the transmitter from outputting too long a packet. The transmitter uses summing resistors and a transformer/filter to output Manchester encoded data. The ENDEC interfaces between either the TPI or the ETHERNET transceiver and the MAC unit. It provides Manchester data encoding and decoding functions for IEEE 802.3 ETHERNET, so called Thin-ETHERNET, or twisted-pair types of LANS. The ENDEC combines non-return to zero (NRZ) data from the MAC unit and clock pulses into Manchester data and sends the data differentially to the transmitter, e.g., in the TPI. During reception, a digital phase locked loop (DPLL) decodes the Manchester data into NRZ-formatted data and into a receive clock. The MAC unit controls media access of transmitting and receiving packets. The MAC unit frames information from a transmit FIFO for transmission and sends serialized data to the ENDEC. The transmit FIFO is arranged as a four-byte wide and eight deep memory array. Incoming information from the ENDEC is deserialized and frame-checked for validity. Received data is transferred to a receive FIFO. The receive FIFO is also arranged as a four-byte wide and eight deep memory array. Control and status registers are used to manage the MAC unit. The host interface of the SONIC chip has two parts, the control part and the data part. The control part consists of sixty-four addressable registers, an interrupt line, a reset signal, and a chip select line. The data part of the interface uses the DMA transfers between the FIFO's in the SONIC chip and the host memory.
In conventional SONIC devices, a content addressable memory (CAM) is included in the MAC receiver to assist an address recognition unit. A CAM address mismatch causes a packet to be rejected whenever the destination address in the packet does not match an address stored in the CAM. When matches do occur, a de-serializer passes a packet remainder to the receive FIFO. A protocol state machine is included in the MAC transmitter to enforce the carrier sense multiple access with collision detection (CSMA/CD) protocol of the ETHERNET. The carrier sense and collision signals are monitored for network activity. Transmission is deferred if the network is busy. Otherwise, an inter-frame gap timer (9.6 microseconds) times-out and transmission begins. Any network activity detected in the first 6.4 microseconds will restart the timer. Otherwise, network activity is ignored and transmission begins at the end of the current 9.6 microsecond period. If a collision with another transmitter is then detected, a four byte jam pattern of all ones is immediately substituted before terminating the failed transmission. A random number of times slots is inserted as a wait period, where each time slot is 51.2 microseconds. A truncated binary exponential back-off algorithm is used to determine when another transmission should be attempted.
Conventional SONIC single-chip devices provide only one network interface per device, and are "one size fits all", in that the same device is marketed for use by network clients and servers alike. This is especially odd in that many clients on a single segment with a server tend to focus their traffic with the server. Thus more bandwidth is needed on the server link than is required for the client links.
ETHERNET switching is a recent technology that provides for the connection of multiple ETHERNET LANs to a central switch. A telephone private branch exchange (PBX) is conceptually similar. Within the ETHERNET switch, paralleled circuit switching allows the simultaneous transport of multiple packets across the switch. Fast-packet switching improves the throughput by reducing packet buffering, e.g., by reading only the destination address part of an ETHERNET packet. Two ETHERNET switches can be inter-tied by a full-duplex ETHERNET connection "FDES", that allows only one transmitter on each connection, therefore eliminating collisions. Since each connection in each of two directions is able to run at the full ten Mbps, an FDES inter-tie is commonly rated for twenty Mbps. Kalpana, Inc. (Sunnyvale, Calif.) is a pioneer in ETHERNET switching technology, and markets products under the ETHERSWITCH trade name.
However, ETHERNET switching, and other conventional technologies do not address the problem of traffic bottle-necking that can occur on each LAN, or LAN segment, at the network interface controller in a LAN adapter on a server.
In addition to the ten Mbps ETHERNET chips, there are two industry groups working on one hundred Mbps ETHERNET using unshielded twisted pair (UTP) based cabling. One group is known as the "Fast ETHERNET Alliance", and is spearheaded by a company called Grand Junction. Its technology is known as the 100-Base-X which uses two pairs of category-five UTP's and a revamped CSMA/CD protocol. The other group is known as the "100VG-AnyLAN group", and is spearheaded by Hewlett-Packard Corporation. This technology uses four pairs of category-three UTP's to achieve a one hundred Mbps speed. An IEEE committee has sanctioned the technology as the "802.12 standard", and its cabling scheme is referred to as the "100-Base-VG standard". Unfortunately, the one hundred Mbps technology requires an expensive new cable system, has been slow in gaining wide acceptance, and the chip sets are not currently available.